Divide one input by another
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Libraries:
Simulink / Math Operations
HDL Coder / HDL Floating Point Operations
HDL Coder / Math Operations
Description
The Divide block outputs the result of dividing its first input by itssecond. The inputs can be scalars, a scalar and a nonscalar, or two nonscalars that havethe same dimensions. This block supports only complex input values at division portswhen all ports have the same single or double data type.
The Divide block is functionally a Product block that has two blockparameter values preset:
Multiplication —
Elementwise(.*)
Number of Inputs —
*/
Setting nondefault values for either of those parameters can change a Divideblock to be functionally equivalent to a Product block or a Product of Elements block.
Examples
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Divide Inputs of Different Dimensions Using the Divide Block
Open Model
This example shows how to perform elementwise (.*)
division of two inputs using the Divide block. In this example, the Divide block divides two scalars, a vector by a scalar, a scalar by a vector, and two matrices.
Ports
Input
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X — Input signal to multiply
scalar  vector  matrix  ND array
Input signal to be multiplied with other inputs.
Dependencies
To enable one or more X ports, specify one ormore *
characters for the Number ofinputs parameter and set theMultiplication parameter toElementwise(.*)
.
Data Types: half
 single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 Boolean
 fixed point
÷ — Input signal to divide or invert
scalar  vector  matrix  ND array
Input signal for division or inversion operations.
Dependencies
To enable one or more ÷ ports, specify one ormore /
characters for the Number ofinputs parameter and set theMultiplication parameter toElementwise(.*)
.
Data Types: half
 single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 Boolean
 fixed point
Port_1 — First input to multiply or divide
scalar  vector  matrix  ND array
First input to multiply or divide, provided as a scalar, vector,matrix, or ND array.
Data Types: half
 single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 Boolean
 fixed point
Port_N — Nth input to multiply or divide
scalar  vector  matrix  ND array
Nth input to multiply or divide, provided as a scalar, vector, matrix,or ND array.
Data Types: half
 single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 Boolean
 fixed point
* — Input signal to multiply
scalar  vector  matrix  ND array
Input signal to be multiplied with other inputs.
Dependencies
To enable one or more * ports, specify one ormore *
characters for the Number ofinputs parameter and set theMultiplication parameter toMatrix(*)
.
Data Types: half
 single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 Boolean
 fixed point
Inv — Input signal to divide or invert
scalar  vector  matrix  ND array
Input signal for division or inversion operations.
Dependencies
To enable one or more Inv ports, specify oneor more /
characters for the Number ofinputs parameter and set theMultiplication parameter toMatrix(*)
.
Data Types: half
 single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 Boolean
 fixed point
Output
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Port_1 — Output computed by multiplying, dividing, or inverting inputs
scalar  vector  matrix  ND array
Output computed by multiplying, dividing, or inverting inputs.
Data Types: half
 single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 Boolean
 fixed point
Parameters
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Main
Number of inputs — Control number of inputs and type of operation
*/
(default)  positive integer scalar  *
or /
for each inputport
Control two properties of the block:
The number of input ports on the block
Whether each input is multiplied or divided into theoutput
When you specify:
1
or*
or/
The block has one input port. In elementwise mode, the blockprocesses the input as described for the Product ofElements block. In matrix mode, if the parametervalue is
1
or*
, the blockoutputs the input value. If the value is/
,the input must be a square matrix (including a scalar as adegenerate case) and the block outputs the matrix inverse. SeeElementWise Mode and Matrix Mode for moreinformation.Integer value > 1
The block has the number of inputs given by the integer value.The inputs are multiplied together in elementwise mode ormatrix mode, as specified by the Multiplication parameter. See ElementWise Mode and Matrix Mode for moreinformation.
Unquoted string of two or more
*
and/
charactersThe block has the number of inputs given by the length of thecharacter vector. Each input that corresponds to a
*
character is multiplied into theoutput. Each input that corresponds to a/
character is divided into the output. The operations occur inelementwise mode or matrix mode, as specified by the Multiplication parameter. See ElementWise Mode and Matrix Mode for moreinformation.
Programmatic Use
Block Parameter:Inputs 
Type: charactervector 
Values:'2'  '*'  '**'  '*/'  '*/*' ... 
Default:'*/' 
Multiplication — Elementwise (.*) or Matrix (*) multiplication
Elementwise(.*)
(default)  Matrix(*)
Specify whether the block performs Elementwise(.*)
or Matrix(*)
multiplication.
Programmatic Use
Block Parameter: Multiplication 
Type: character vector 
Values: 'Elementwise(.*)'  'Matrix(*)' 
Default: 'Elementwise(.*)' 
Apply over — How to apply function along specified dimensions
All dimensions
(default)  Specified dimension
Specify how to apply the function along specified dimensions.
All dimensions
— Apply function for all input values for all dimensions.Specified dimension
— Apply function for all input values for specified dimension.
For example, in this model, Multiplication is set to Elementwise(.*)
, and Apply over is set to All dimensions
. The block returns the product of all values from all dimensions.
Dependencies
To enable this parameter, set Number of inputs to *
and Multiplication to Elementwise (.*)
.
Programmatic Use
Block Parameter: CollapseMode 
Type: character vector 
Values: 'All dimensions'  'Specified dimension' 
Default: 'All dimensions' 
Dimension — Dimension along which to multiply
1
(default)  positive integer
Specify the dimension along which to multiply, as a positive integer. For example, for a 2D matrix, 1
applies the function to each column, and 2
applies the function to each row.
For example, in this model, Multiplication is set to Elementwise(.*)
, Apply over is set to Specified dimension
, and Dimension is set to 2
. The block returns the product of all values from each row.
Dependencies
To enable this parameter:
Set Number of inputs to
*
Set Multiplication to
Elementwise (.*)
Set Apply over to
Specified dimension
Programmatic Use
Block Parameter: CollapseDim 
Type: character vector 
Values: '1'  '2'  ... 
Default: '1' 
Sample time (1 for inherited) — Interval between samples
1
(default)  scalar  vector
Specify the time interval between samples. To inherit the sample time, set this parameter to 1
. For more information, see Specify Sample Time.
Dependencies
This parameter is visible only if you set it to a value other than 1
. To learn more, see Blocks for Which Sample Time Is Not Recommended.
Programmatic Use
Block Parameter: SampleTime 
Type: string scalar or character vector 
Default: "1" 
Signal Attributes
Require all inputs to have the same data type — Require that all inputs have the same data type
off
(default)  on
Specify if input signals must all have the same data type. If you enable this parameter, then an error occurs during simulation if the input signal types are different.
Programmatic Use
Block Parameter: InputSameDT 
Type: character vector 
Values: 'off'  'on' 
Default: 'off' 
Output minimum — Minimum output value for range checking
[]
(default)  scalar
Lower value of the output range that Simulink^{®} checks.
Simulink uses the minimum to perform:
Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.
Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).
Automatic scaling of fixedpoint data types.
Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).
Note
Output minimum does not saturate or clip the actual output signal. Use the Saturation block instead.
Programmatic Use
Block Parameter: OutMin 
Type: character vector 
Values: '[ ]'  scalar 
Default: '[ ]' 
Output maximum — Maximum output value for range checking
[]
(default)  scalar
Upper value of the output range that Simulink checks.
Simulink uses the maximum value to perform:
Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.
Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).
Automatic scaling of fixedpoint data types.
Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).
Note
Output maximum does not saturate or clip the actual output signal. Use the Saturation block instead.
Programmatic Use
Block Parameter: OutMax 
Type: character vector 
Values: '[ ]'  scalar 
Default: '[ ]' 
Output data type — Specify the output data type
Inherit: Inherit via internal rule
(default)  Inherit: Inherit via back propagation
 Inherit: Same as first input
 double
 single
 int8
 uint8
 int16
 uint16
 int32
 uint32
 int64
 uint64
 fixdt(1,16)
 fixdt(1,16,0)
 fixdt(1,16,2^0,0)
 <data type expression>
Choose the data type for the output. The type can be inherited, specified directly, or expressed as a data type object such as Simulink.NumericType
. For more information, see Control Data Types of Signals.
When you select an inherited option, the block behaves as follows:
Inherit: Inherit via internal rule
— Simulink chooses a data type to balance numerical accuracy, performance, and generated code size, while taking into account the properties of the embedded target hardware. If you change the embedded target settings, the data type selected by the internal rule might change. For example, if the block multiplies an input of typeint8
by a gain ofint16
andASIC/FPGA
is specified as the targeted hardware type, the output data type issfix24
. IfUnspecified (assume 32bit Generic)
, in other words, a generic 32bit microprocessor, is specified as the target hardware, the output data type isint32
. If none of the word lengths provided by the target microprocessor can accommodate the output range, Simulink software displays an error in the Diagnostic Viewer.It is not always possible for the software to optimize code efficiency and numerical accuracy at the same time. If the internal rule doesn’t meet your specific needs for numerical accuracy or performance, use one of the following options:
Specify the output data type explicitly.
Use the simple choice of
Inherit: Same as input
.Explicitly specify a default data type such as
fixdt(1,32,16)
and then use the FixedPoint Tool to propose data types for your model. For more information, see fxptdlg (FixedPoint Designer).To specify your own inheritance rule, use
Inherit: Inherit via back propagation
and then use a Data Type Propagation block. Examples of how to use this block are available in the Signal Attributes library Data Type Propagation Examples block.
Inherit: Inherit via back propagation
— Use data type of the driving block.Inherit: Same as first input
— Use data type of first input signal.
Dependencies
When input is a floatingpoint data type smaller than single precision, the Inherit: Inherit via internal rule
output data type depends on the setting of the Inherit floatingpoint output type smaller than single precision configuration parameter. Data types are smaller than single precision when the number of bits needed to encode the data type is less than the 32 bits needed to encode the singleprecision data type. For example, half
and int16
are smaller than single precision.
Programmatic Use
Block Parameter: OutDataTypeStr 
Type: character vector 
Values: 'Inherit: Inherit via internal rule  'Inherit: Same as first input'  'Inherit: Inherit via back propagation'  'double'  'single'  'int8'  'uint8'  'int16'  'uint16'  'int32'  'uint32'  'int64'  'uint64'  'fixdt(1,16)'  'fixdt(1,16,0)'  'fixdt(1,16,2^0,0)'  '<data type expression>' 
Default: 'Inherit: Inherit via internal rule' 
Lock output data type setting against changes by the fixedpoint tools — Option to prevent fixedpoint tools from overriding Output data type
off
(default)  on
Select this parameter to prevent the fixedpoint tools from overriding the Output data type you specify on the block. For more information, see Use Lock Output Data Type Setting (FixedPoint Designer).
Programmatic Use
Block Parameter: LockScale 
Type: character vector 
Values: 'off'  'on' 
Default: 'off' 
Integer rounding mode — Rounding mode for fixedpoint operations
Floor
(default)  Ceiling
 Convergent
 Nearest
 Round
 Simplest
 Zero
Select the rounding mode for fixedpoint operations. You canselect:
Ceiling
Rounds positive and negative numbers toward positiveinfinity. Equivalent to the MATLAB^{®}
ceil
function.Convergent
Rounds number to the nearest representable value. If a tieoccurs, rounds to the nearest even integer. Equivalent tothe FixedPoint Designer™
convergent
function.Floor
Rounds positive and negative numbers toward negativeinfinity. Equivalent to the MATLAB
floor
function.Nearest
Rounds number to the nearest representable value. If a tieoccurs, rounds toward positive infinity. Equivalent to theFixedPoint Designer
nearest
function.Round
Rounds number to the nearest representable value. If a tieoccurs, rounds positive numbers toward positive infinity androunds negative numbers toward negative infinity. Equivalentto the FixedPoint Designer
round
function.Simplest
Chooses between rounding toward floor and rounding towardzero to generate rounding code that is as efficient aspossible. This rounding mode is affected by theseconfiguration parameters on the HardwareImplementation pane.
If the Signed integer division roundsto parameter is set to
Zero
orUndefined
,Simplest
resolves tozero.If the Signed integer division roundsto parameter is set to
Floor
,Simplest
resolves tofloor
.
Zero
Rounds number toward zero. Equivalent to the MATLAB
fix
function.
For more information, see Rounding (FixedPoint Designer).
Block parameters always round to the nearest representable value. Tocontrol the rounding of a block parameter, enter an expression using aMATLAB rounding function into the mask field.
Programmatic Use
Block Parameter:RndMeth 
Type: charactervector 
Values:'Ceiling'  'Convergent'  'Floor'  'Nearest' 'Round'  'Simplest'  'Zero' 
Default:'Floor' 
Saturate on integer overflow — Method of overflow action
off
(default)  on
Specify whether overflows saturate or wrap.
Action  Rationale  Impact on Overflows  Example 

Select this check box (  Your model has possible overflow, and you want explicit saturation protection in the generated code.  Overflows saturate to either the minimum or maximum value that the data type can represent.  The maximum value that the 
Do not select this check box (  You want to optimize efficiency of your generated code. You want to avoid overspecifying how a block handles outofrange signals. For more information, see Troubleshoot Signal Range Errors.  Overflows wrap to the appropriate value that is representable by the data type.  The maximum value that the 
When you select this check box, saturation applies to every internal operation on the block, not just the output, or result. Usually, the code generation process can detect when overflow is not possible. In this case, the code generator does not produce saturation code.
Programmatic Use
Block Parameter: SaturateOnIntegerOverflow 
Type: character vector 
Values: 'off'  'on' 
Default: 'off' 
Mode — Select data type mode
Inherit
(default)  Built in
 Fixed Point
Select the category of data to specify.
Inherit
— Inheritance rules for data types. SelectingInherit
enables a second menu/text box to the right where you can select the inheritance mode.Built in
— Builtin data types. SelectingBuilt in
enables a second menu/text box to the right where you can select a builtin data type.Fixed point
— Fixedpoint data types. SelectingFixed point
enables additional parameters that you can use to specify a fixedpoint data type.Expression
— Expressions that evaluate to data types. SelectingExpression
enables a second menu/text box to the right, where you can enter the expression.
For more information, see Specify Data Types Using Data Type Assistant.
Dependencies
To enable this parameter, click the Show data type assistant button.
Data type override — Specify data type override mode for this signal
Inherit
 Off
Select the data type override mode for this signal.
When you select
Inherit
, Simulink inherits the data type override setting from its context, that is, from the block,Simulink.Signal
object or Stateflow^{®} chart in Simulink that is using the signal.When you select
Off
, Simulink ignores the data type override setting of its context and uses the fixedpoint data type specified for the signal.
For more information, see Specify Data Types Using Data Type Assistant in the Simulink documentation.
Dependencies
To enable this parameter, set Mode to Built in
or Fixed point
.
Tips
The ability to turn off data type override for an individual data type provides greater control over the data types in your model when you apply data type override. For example, you can use this option to ensure that data types meet the requirements of downstream blocks regardless of the data type override setting.
Signedness — Specify signed or unsigned
Signed
(default)  Unsigned
Specify whether the fixedpoint data is signed or unsigned. Signed data can represent positive and negative values, but unsigned data represents positive values only.
Signed
, specifies the fixedpoint data as signed.Unsigned
, specifies the fixedpoint data as unsigned.
For more information, see Specify Data Types Using Data Type Assistant.
Dependencies
To enable this parameter, set the Mode to Fixed point
.
Word length — Bit size of the word that holds the quantized integer
16
(default)  integer from 0 to 32
Specify the bit size of the word that holds the quantized integer. For more information, see Specifying a FixedPoint Data Type.
Dependencies
To enable this parameter, set Mode to Fixed point
.
Fraction length — Specify fraction length for fixedpoint data type
0
(default)  scalar integer
Specify fraction length for fixedpoint data type as a positive or negative integer. For more information, see Specifying a FixedPoint Data Type.
Dependencies
To enable this parameter, set Scaling to Binary point
.
Scaling — Method for scaling fixedpoint data
Best precision
(default)  Binary point
 Slope and bias
Specify the method for scaling your fixedpoint data to avoid overflow conditions and minimize quantization errors. For more information, see Specifying a FixedPoint Data Type.
Dependencies
To enable this parameter, set Mode to Fixed point
.
Slope — Specify slope for the fixedpoint data type
2^0
(default)  positive, realvalued scalar
Specify slope for the fixedpoint data type. For more information, see Specifying a FixedPoint Data Type.
Dependencies
To enable this parameter, set Scaling to Slope and bias
.
Bias — Specify bias for the fixedpoint data type
0
(default)  realvalued scalar
Specify bias for the fixedpoint data type as any real number. For more information, see Specifying a FixedPoint Data Type.
Dependencies
To enable this parameter, set Scaling to Slope and bias
.
Block Characteristics
Data Types 

Direct Feedthrough 

Multidimensional Signals 

VariableSize Signals 

ZeroCrossing Detection 

Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Expected Differences Between Simulation and Code Generation
These conditions may yield different results between simulation and thegenerated code:
The Divide block inputs contain a
NaN
orinf
valueThe Divide block generates
NaN
orinf
during execution
This difference is due to the nonfinite NaN
orinf
values. In such cases, inspect your modelconfiguration and eliminate the conditions that produce NaN
or inf
.
Code Optimizations
The Simulink Coder™ build process provides efficient code for matrix inverse anddivision operations. This table describes the benefits and when each benefit isavailable.
Benefit  Small Matrices (2by2 to5by5)  Medium Matrices (6by6 to20by20)  Large Matrices (larger than20by20) 

Faster code execution time, compared to R2011a and earlierreleases  Yes  No  Yes 
Reduced ROM and RAM usage, compared to R2011a and earlierreleases  Yes, for real values  Yes, for real values  Yes, for real values 
Reuse of variables  Yes  Yes  Yes 
Dead code elimination  Yes  Yes  Yes 
Constant folding  Yes  Yes  Yes 
Expression folding  Yes  Yes  Yes 
Consistency with MATLAB Coder results  Yes  Yes  Yes 
For blocks that have three or more inputs of different dimensions, the codemight include an extra buffer to store temporary variables for intermediateresults.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDLimplementation and synthesized logic.
Note
When you deploy the generated HDL code onto the target hardware, make surethat you set the signed integer division rounds toparameter in the Hardware Implementation pane of theConfiguration Parameters dialog box to Zero
orFloor
.
To perform an HDLoptimized divide operation, connect a Productblock to a Divide block in reciprocal mode.
HDL Architecture
The Divide block is the same as a Product blockwith Number of Inputs set to */
.
Architecture  Parameters  Additional cycles of latency  Description 

ShiftAdd(Default)  None  Depends on wordlength and fractionallength of inputand output. For more information, see  Perform divide operations by using a nonrestoring division algorithm thatperforms multiple shift and add operations to compute thequotient. When you use fixedpoint data types,following criteria must be satisfied for generating the HDLcode:

Reciprocal Mode
When Number of Inputs is set to /
, theDivide block is in reciprocal mode.
This block has multicycle implementations that introduce additionallatency in the generated code. To see the added latency, view thegenerated model or validation model. See Generated Model and Validation Model (HDL Coder).
In reciprocal mode, the Divide block has the HDL block implementationsdescribed in the following table.
Architectures  Parameters  Additional cycles of latency  Description 

ShiftAdd(Default)  None  Depends on wordlength and fractionallength of input and output. For moreinformation, see  Perform reciprocal operation by using a nonrestoring divisionalgorithm that performs multiple shift and addoperations to compute the reciprocal. Whenyou use fixedpoint data types, following criteria mustbe satisfied for generating the HDL code:

HDL code generation supports different output data types for divide(*/)
and reciprocal (/)
operations inShiftAdd
. You can use these output data types forthe blocks:
Inherit: Inherit via internalrule
Inherit: Keep MSB
Inherit: Match scaling
Inherit: Inherit via backpropagation
Inherit: Same as first input
Integer types(uint8,int8,uint16,int16,uint32,int32,uint64,int64)
Fixed point types
HDL Block Properties
General  

ConstrainedOutputPipeline  Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 
InputPipeline  Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 
OutputPipeline  Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 
LatencyStrategy  To enable this property, set HDL architecture to 
CustomLatency  To enable this property, set HDL architecture to 
Native Floating Point  

HandleDenormals  Specify whether you want HDL Coder to insert additional logic to handle denormal numbers in your design. Denormal numbers are numbers that have magnitudes less than the smallest floatingpoint number that can be represented without leading zeros in the mantissa. The default is 
MantissaMultiplyStrategy  Specify how to implement the mantissa multiplication operation during code generation. By using different settings, you can control the DSP usage on the target FPGA device. The default is 
DivisionAlgorithm  Specify whether to use the Radix2 or Radix4 algorithm to perform the floatingpoint division. The Radix2 mode offers a tradeoff between latency and frequency. The Radix4 mode offers a tradeoff between latency and resource usage. For more information, see DivisionAlgorithm (HDL Coder). 
Complex Data Support
This block does not support code generation for division withcomplex signals.
Optimization Support
You can apply the sharing or streaming optimizations for Divide and Reciprocalblocks using ShiftAdd
architecture.
Block (Inputs)  Resource Sharing  Streaming 

Divide(/* or */)  Yes  Yes 
Reciprocal (/)  Yes  No 
For more information, see Resource Sharing (HDL Coder) and Streaming (HDL Coder).
Restrictions
When you use the Divide block in reciprocal mode, the followingrestrictions apply:
When you use fixedpoint types, the input and output must be scalar.To use vector inputs, use floatingpoint types input and output.
You must select the Saturate on integer overflowoption on the block.
For the Divide block, only the Zero
and Simplest
rounding modes are supported.
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
FixedPoint Conversion
Design and simulate fixedpoint systems using FixedPoint Designer™.
Version History
Introduced before R2006a
See Also
Product  Dot Product  Product of Elements
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